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fifo
- fifo designed by haneesh (me) in verilog-fifo designed by haneesh (me) in verilog
fifo
- 采用verilog HDL语言实现FIFO的功能，内涵测试程序，有较强的使用性能。-Using verilog HDL language to achieve FIFO functionality, meaning the test program, there is a strong performance.
FIFO
- 此程序为verilog语言，实现的功能为FIFO功能，包括三个部分，分别实现不同的功能。-This program is verilog language, functions as a FIFO function, consists of three parts, respectively, to achieve different functions.
FIFO
- verilog 实现FIFO存储功能，八位数据宽度，16数据深度。-verilog achieve FIFO memory functions, eight-bit data width, the depth of 16 data.
fifo
- 使用verilog实现FIFO，包含所有工程文件。-Verilog implementation using FIFO, includes all project files.
FIFO-Design
- FIFO(first in first out)-first in first out, using verilog
Verilog-FIFO
- 可综合的Verilog FIFO存储器，可以实现先如先出的设计-Synthesizable Verilog FIFO memory can be as-first-out design
USB_FPGA
- 基于Cyclone EP3C25的USB与CY60183传递数据的FIFO Verilog HDL源代码（FPGA端程序）-The program is a communication source code about USBCyclone EP3C25 transfering data via FIFO with CY60183 (only FPGA source code(verilog HDL) is included)
fifo_4X16
- 完整的FIFO Verilog程序，经过仿真验证，直接可用-FIFO Verilog
Asynchronous-FIFO-Design
- 异步FIFO设计，一共包含6个模块，使用的硬件描述语言verilog。-Asynchronous FIFO design,including six modules.HDL language is verilog.
FIFO
- FIFO的设计，用Verilog HDL语言编写-The design of FIFO,using Verilog HDL program language
FIFO
- Verilog代码，实现FIFO先入先出存储-FIFO CODE,VERILOG
afifo
- verilog HDL fifo , verilog HDL fifo , -verilog HDL fifo ,verilog HDL fifo ,verilog HDL fifo ,verilog HDL fifo ,
NANDFlashcontrolandFIFOcontrol
- 实现NAND Flash块的控制存取以及同步的FIFO的控制 verilog 代码-NAND Flash control access and control of the synchronous FIFO verilog code
5-verilog-programs
- the file contains 5 verilog source codes 1. varying pulses 2. DRAM 3. FIFO 4. UART 5. 16 bit divider
Example1
- fifo verilog hdl along with test bench its hardware
fifo
- 采用verilog语言的fifo设计。用notpad编辑-Verilog language fifo design. Edited using notpad
10_100m_ethernet-fifo
- 本源码源自于网络，采用verilog编写完成10M以太网到100M以太网的FIFO转化。-The source from the network, using verilog written 10M Ethernet 100M Ethernet FIFO conversion.
fifo_module
- verilog 语言写的FIFO历程，可以很好参考。 -The write FIFO verilog language course, a good reference.
FIFO
- FIFO is accomplished with the code which is written using the language of verilog.FIFO is the means of first output while first input